
H200 SXM5 · 141 GB
The Hopper refresh. Same compute, 76% more memory bandwidth than H100. The sweet spot for 70B / 8B-class models at 8k–128k context.
Pick a model and a GPU. Get VRAM fit, throughput, max concurrent sequences, and a ready-to-run vLLM command.
Strong general-purpose. ~140 GB at FP16.
8 GPUs per node via NVLink + IB · 80 GB VRAM · 495 BF16 TFLOPS · 3,350 GB/s BW
Half the VRAM. ~99% quality retention.
# vLLM — Llama 3.1 70B on 1× H100 # Pricing: ~$2.40/hr · ~$1752/mo 24/7 docker run --gpus all --shm-size 1g \ -p 8000:8000 \ -v ~/.cache/huggingface:/root/.cache/huggingface \ vllm/vllm-openai:latest \ --model llama-3.1-70b \ --tensor-parallel-size 1 \ --max-model-len 4096 \ --quantization fp8 \ --gpu-memory-utilization 0.92
Tensor-parallel = 1. Adjust --max-model-len and --gpu-memory-utilization for your batch / latency tradeoff.
Pick H100s, H200s, B200s, GB200 racks, and Cerebras CS-3 systems in any combination. See the run cost on SmartTec, what you could rent it for, and your gross margin — all live. Phase 2/3 cost-alternative track: AMD Instinct MI455X (432 GB HBM4, 19.6 TB/s — 2.4× the memory bandwidth of B200) is now selectable in the fit-check for planning; priced configurations publish once OEM availability and ROCm serving mature.
What you see below is what SmartTec actually runs. Three NVIDIA systems + one wafer-scale engine, on the same power fabric.

The Hopper refresh. Same compute, 76% more memory bandwidth than H100. The sweet spot for 70B / 8B-class models at 8k–128k context.

The Blackwell baseboard. 8× B200 SXM, 1.5 TB total HBM3e per board. Where most frontier inference starts.

A single rack. 36 Grace CPUs, 72 Blackwell GPUs, one NVLink domain. What trillion-parameter inference runs on.

One chip, one wafer, one system. The largest silicon ever built. Per-1K-token billing, not per-hour.

What a CS-3 actually looks like in a rack. Pink fiber = wafer-scale fabric. Front mesh = the cooling intake.

The wafer on the left holds one die. The wafer on the right is the entire NVIDIA B200 chip, scaled up for visibility.
NVIDIA hardware photography sourced from nvidia.com/data-center (NVIDIA press kit, public marketing assets). Cerebras hardware photography sourced from cerebras.ai (CS-3 product page, public marketing assets). The wafer-vs-B200 scale comparison is from the Cerebras WSE-3 announcement. These exact systems deploy at our Mead, OK facility at Q4 2026 power-on.
Llama 3 70B at FP16 = 70B × 2 bytes = 140 GB. Quantized to FP8 = 70 GB. We add a 5% buffer for activations and CUDA kernels.
Per sequence at seq_len ℓ and batch B. Llama 3 70B at 8k context, batch 8 = ~10 GB. Linear in batch size.
Decode is memory-bound: tokens/s ≈ BW / (params × bytes). Prefill is compute-bound: tokens/s ≈ TFLOPS / (2 × params). We take the minimum.
config.json on HuggingFace.Send this fit-check to partners@smarttec.dev. We'll send back a deployment plan, Q4 2026 power-on target, and design-partner pricing locked for 12 months.